ASIC Design & Verification


We offer solutions for the development and verification of ASICs. This covers traditional simulation based techniques as well as the use of static and formal based methods. Due to our own individual backgrounds, our team has specialist knowledge of ASIC Design & Verification which when coupled with that of our suppliers, allows us to provide valuable and independent guidance.

Driven by the large NRE and TTM pressures of consumer electronics, it’s vital that an ASIC is right first time. This has resulted in the task of verification closure becoming critical for success of the project and in many cases the company. For this reason new methods to improve overall coverage and efficiency are being adopted by leading ASIC project teams.

Advanced Design Rule Checking / FPGA / FV / SAFETY / ASIC

ALINT-PRO is a design rule checking (DRC) tool. It uses rule files (‘policies’) to check that a design’s RTL adheres to a defined RTL coding style. It decreases development time dramatically by identifying design issues early in the development schedule.

Aldec Riviera-PRO
Advanced Verification Platform / FPGA / FV / ASIC

Riviera-PRO addresses the verification requirements of engineers targeting large gate-count FPGAs, ASICs and System-on-Chip devices. It gives engineers the ultimate testbench in terms of productivity, reusability and automation; all by combining a high-performance simulation engine with advanced debugging capabilities (at different levels of abstraction).

Advanced Design Rule Checking / FPGA / FV / SAFETY / ASIC

ALINT-PRO-CDC is a design verification solution focused on asynchronous clock domain crossing analysis and used to manage metastability in designs with multiple clock domains.

Hardware Assisted Verification / HW-V / PROTO / ASIC

HES-DVM is a fully automated verification and validation system for SoC ASIC designs of 200M+ ASIC gates. Aldec’s FPGA Hardware Emulation Solution is based on the latest Xilinx Virtex-7 devices and is capable of simulation acceleration, and SCE-MI transaction co-emulation.

Aldec HES-7
ASIC Prototyping / HW-V / PROTO / ASIC

HES-7 provides SoC and ASIC verification and validation teams with a scalable and high-quality FPGA-based ASIC prototyping solution. Each HES-7 board with dual Xilinx Virtex-7 2000T has 4million FPGA logic cells (or up to 24million ASIC gates of capacity) not including the DSP and memory resources.

Sigasi Studio
VHDL code editing, browsing & checking / FPGA / SAFETY / ASIC

The Sigasi Studio platform was developed specifically to make HDL design easier and more efficient. It is based on the Eclipse platform and brings the same kind of real-time code checking assistance that software engineers have enjoyed for years firmly into the hardware arena.