Sigasi Visual HDL
HDL CODE EDITING, BROWSING & CHECKING / FPGA / SAFETY / ASIC
HDL CODE EDITING, BROWSING & CHECKING / FPGA / SAFETY / ASIC
Founded in 2008, Sigasi is a privately funded company based in Belgium. Sigasi’s mission is to pioneer a new era of chip development, prioritising user experience and unwavering design integrity, empowering hardware designers to achieve excellence in HDL creation, integration, and validation.
Sigasi has partnerships with key FPGA vendors (including Altera and Xilinx) and leading EDA companies (including Aldec) and its platform is being used by some of the biggest names in aerospace, defence, consumer electronics, industrial automation, medical electronics and telecom.
SVH is an HDL platform, the place where chip designers and verification engineers can shift their hardware design language (HDL) and register transfer language (RTL) projects to the left. (Find out more about what “shifting left” means in our FAQ section !)
Fully integrated within the leading integrated development environment (VS Code ), SVH harnasses the rich marketplace of existing tools like source control management (SCM), central repositories, gremlin tracking, bookmarks, and comment-based TODO lists.
To make life even easier, SVH gives you tiered editions that build on each other in a single extension. One download, many license options.
Each edition uses industry standards to ensure you get the highest quality checks as you create your code, with specific language and standards support.
Create with type-time syntax and semantic checks; guardrails that enforce coding styles, policies, and standards; and instant feedback and warnings for any files associated with a project.
Moreover, Sigasi offers numerous ways to view a project, all updated in real-time (no need to save first) and with cross-probing. Move seamlessly through hierarchy views and graphics that update instantaneously as you make changes in your code.
How does it work?
Sigasi users who have a commercial license for our older products can seamlessly transition to SVH, just input your existing license information.
HDL (VHDL/SystemVerilog) design can be difficult and complex and Sigasi Visual HDL is a design creation tool that helps deal with that complexity. Sigasi Visual HDL makes your hardware design:
Easier_ A basic text editor just won’t do if you want to write code like a pro. Sigasi Visual HDL is an intelligent design tool that offers advanced design assistance. Why walk if you can drive… or get driven to your destination? | |
More efficient_ Sigasi Visual HDL guides you through complex code designs. With instant feedback on errors and auto-completion suggestions. Reducing development time and helping you and your team write better code. | |
Faster_ Sigasi’s secret ingredient is the super fast built-in compiler. Because Sigasi Visual HDL understands your code whilst you type, it can help you be more productive, produce higher quality work and excel in your work. |
Sigasi Visual HDL is like your personal assistant. It provides you with:
Code editing_ Code completion, including component instantiations, based on where you are in the code. Sigasi Visual HDL marks your syntax errors as you type, so you can fix them right away. The code is formatted and beautified consistently. | |
Code browsing_ Sigasi Visual HDL serves as a code browser, so that you can navigate through your designs to understand large and complex legacy designs. With graphical browsing you can create visuals of your code, updated instantly and cross-linked to your code. | |
Code checking_ See errors whilst you type and get warnings about dubious code. You will be more efficient as you need less time to write better code, and you are able to free up valuable time at code reviews. | |
Documentation_ Generate complete state machine diagrams or block diagrams that are always up-to-date. Text for documentation can be written as inline comments. |
Features Matrix | DESIGNER EDITION For the individual designer |
PROFESSIONAL EDITION For the serious commercial designer |
ENTERPRISE EDITION For the entire team |
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INTROSPECTION | |||
CodeAssist (All the must-have language and HDL-specific features) |
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• Hovers | |||
• Autocomplete | |||
• Semantic Highlighting | |||
• Occurrence Highlighting | |||
• (Quick) Outline | |||
• Progress Reporting | |||
• Syntax Errors | |||
• Structural Selection | |||
• Open Design Unit | |||
• Goto Implementation | |||
• Configurable Formatting | |||
• Class Hierarchy | |||
• Hierarchy View | |||
• Folding | |||
• Task View | |||
• Libraries View | |||
ComplianceAssist (Smart HDL-specific features that go above and beyond) |
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• Linting | |||
• Quick Fixes | |||
DesignAssist (compliance to required standards such as DO-254) |
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• Signature Helper | |||
• Semantic Errors | |||
• Rename Refactoring | |||
• Net Search | |||
• Template Autocomplete | |||
• Preprocessor View | |||
VERIFICATION and VISUALIZATION | |||
GraphicAssist (Graphical views to help you understand your HDL code) |
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• Dependencies View | |||
• Block Diagram View | |||
• State Machines View | |||
• Documentation View | |||
VerificationAssist (All you need for the UVM verification framework) |
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• UVM Linting | |||
• UVM Topology View | |||
• UVM Diagram | |||
CLI AUTOMATION and DOCUMENTATION | |||
TaskAssist (All project information, easily and quickly extracted in CI/CD) |
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• CLI Lint Reporting | |||
• CLI Dependency Generation | |||
• CLI Diagram Generation | |||
DocAssist (Automated documentation generation extracted from your source code) |
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• Documentation Generation |
With a dedicated development team and through close relationships with their users and partners, Sigasi are constantly working to evolve the tool and build on its capabilities. The result is regular quarterly software releases, ensuring that the latest HDL standards, agile methods and verification methodologies are supported.
VIDEO: Sigasi Visual HDL Integration
BLOG: Sigasi – Hardware Design Made Easier, More Efficient And More Fun