Online VHDL Training

FirstEDA provide high-quality instructor-led in-person and online live training in languages and methodologies, as well as tool proficiency. Our interactive courses and workshops are developed and delivered by our own highly experienced engineers or through our long-standing partnership with industry-renowned VHDL specialist Jim Lewis, of SynthWorks, who actively contributes to IEEE VHDL standards and the Open Source VHDL Verification Methodology (OSVVM).

Full Details/Reserve Your Place

VHDL for FPGA Designers


This instructor-led online training course provides a thorough background in the use and application of synthesisable VHDL in digital hardware design.

Intermediate VHDL


Ready for the next step? For those already familiar with VHDL (either through introductory training or self-taught), this online course will broaden knowledge and enforce competency through application.

Essential VHDL Verification


You will learn to create structured transaction-based testbenches using either procedures or models (aka: verification IP or transaction level models). Both of these methods facilitate creation of simple, powerful, and readable tests.

Advanced VHDL Testbenches & Verification


Developed and delivered online by VHDL specialist Jim Lewis, you will gain the knowledge needed to improve your verification productivity and create a VHDL testbench environment competitive with other verification languages, such as SystemVerilog (UVM).

Meet The Trainers

David Clift - Applications Specialist at FirstEDA David Clift – Lead Trainer 


As well as developing and delivering our language and tool training, David is an Application Specialist at FirstEDA. David’s 30+ year electronics engineering career started at GEC Marconi 1984, where he worked as an electronics engineer before making the move to EDA in 1994. He has extensive experience in the development and use of HDL tools in both practical and training environments.
David’s widespread knowledge of the industry and it’s technology, languages and tools has enabled FirstEDA to deliver unique learning labs, with multiple tools to help meet your design challenges.


Jim Lewis - SynthWorks Jim Lewis – Training Partner, Verification & Methodology


Jim is the founder and Principal Trainer at US based VHDL training specialists, SynthWorks. Jim has over thirty years of design teaching and problem solving experience. In addition, Jim is a seasoned ASIC and FPGA Design & Verifcation engineer, with many years of experience in custom model development and consulting. He is a founder of the Open Source VHDL Verifcation Methodology (OSVVM) and the principal architect of its packages and methodology. Jim is also chair of the IEEE 1076 VHDL Analysis and Standardization Working Group (VASG) and is an active member in IEEE and the VHDL standardisation efforts.