Riviera-PRO addresses the verification requirements of engineers targeting large gate-count FPGAs, ASICs and System-on-Chip devices. It gives engineers the ultimate testbench in terms of productivity, reusability and automation; all by combining a high-performance simulation engine with advanced debugging capabilities (at different levels of abstraction).
Riviera-PRO is a high performance, high capacity, multi-language simulator that provides a unified debug environment for VHDL, Verilog, SystemVerilog, SystemC and PSL. The core simulation engine includes advanced simulation optimisation for both VHDL & Verilog simulation.
As well as supporting traditional HDL verification techniques, Riviera-PRO provides advanced analysis and debug capabilities for UVM and TLM verification methodologies.
Riviera-PRO provides project and workspace capability as well as script-based operation for compilation and simulation.
Riviera-PRO is an extremely capable EDA solution, with all the features that you would expect to see on a high-end verification tool.