FPGA Design & Verification - FirstEDA
page-template-default,page,page-id-19040,page-child,parent-pageid-18486,ajax_fade,page_not_loaded,,qode-child-theme-ver-1.0.0,qode-theme-ver-14.5,qode-theme-bridge,wpb-js-composer js-comp-ver-6.2.0,vc_responsive

FPGA Design & Verification


We promote, support and can provide training for a number of highly efficient and cost-effective solutions for FPGA design and verification. These solutions provide excellent views over and into your designs and automate essential tasks.

FPGAs have come an incredibly long way since their introduction in the mid-1980s. While low gate-count devices are still used extensively at one end of the spectrum we now have broad availability of multi-million gate FPGAs with embedded processor cores. Accordingly, the automation of design and verification tasks is essential if projects are to be completed on time and, importantly, with confidence.

Aldec Active-HDL
FPGA Design & Simulation / FPGA / FV

Active-HDL is a Windows-based, integrated design creation and simulation solution for engineers working on projects ranging from simple PLD ‘glue logic’ all the way up to several-million-gate system-on-chip FPGAs.

Advanced Design Rule Checking / FPGA / FV / SAFETY / ASIC

ALINT-PRO is a design rule checking (DRC) tool. It uses rule files (‘policies’) to check that a design’s RTL adheres to a defined RTL coding style. It decreases development time dramatically by identifying design issues early in the development schedule.

Aldec Riviera-PRO
Advanced Verification Platform / FPGA / FV / ASIC

Riviera-PRO addresses the verification requirements of engineers targeting large gate-count FPGAs, ASICs and System-on-Chip devices. It gives engineers the ultimate testbench in terms of productivity, reusability and automation; all by combining a high-performance simulation engine with advanced debugging capabilities (at different levels of abstraction).

Advanced Design Rule Checking / FPGA / FV / SAFETY / ASIC

ALINT-PRO-CDC is a design verification solution focused on asynchronous clock domain crossing analysis and used to manage metastability in designs with multiple clock domains.

Prototyping Microsemi Rad Tolerant Devices / FPGA / PROTO

Aldec and Microsemi have joined forces to offer an innovative, reprogrammable prototyping solution for Microsemi RTAX-S/SL, RTAX-DSP and RTSX-SU space-fight system designs. Unlike the traditional One Time Programmable (OTP) anti-fuse space-qualified FPGAs, the Aldec prototype adaptor uses flash-based, Microsemi ProASIC 3E FPGA technology for design prototype re-programmability.

Concept Engineering StarVision PRO
Debugging & visualisation of mixed signal & digital designs / FPGA / ASIC

StarVision PRO is an RTL-, gate- and SPICE-level integrated debugging and visualisation tool. It has been developed to help electronics engineers cope with the increasing use of building blocks in SoC designs, by allowing them to work at different design levels of abstraction (RTL, gate, transistor, analogue and parasitics) as well as with different design languages and netlist formats.

Concept Engineering RTLvision PRO
Debugging & visualisation of RTL code / FPGA / ASIC

RTLvision PRO provides easy RTL debugging and fast visualisation of RTL code, enabling engineers to implement and optimise VHDL, Verilog or SystemVerilog code.

Concept Engineering GateVision PRO
Gate-level netlist viewing & debugging / FPGA / ASIC

GateVision PRO is a graphical gate-level netlist analyser and netlist viewer. It provides designers working on even the largest ICs and SoCs with intuitive design navigation, netlist viewing, waveform viewing, logic cone extraction, interactive logic cone viewing for netlist debugging and design documentation.

OneSpin Solutions 360 DV-Inspect
Automated Static Analysis / FPGA / FV / SAFETY / ASIC

360 DV-INSPECT increases the productivity of existing design and verification flows by adding push-button formal analysis; which can start as soon as the design under test (DUT) has been compiled, and independently of testbenches. In this way, critical bugs can be found much earlier than with a purely simulation-based flow.

OneSpin Solutions 360 DV-Verify
Assertion-based Verification / FPGA / FV / SAFETY / ASIC

360 DV-Verify is a unified coverage-driven assertion-based verification solution. The combination of a fully functional, high-performance formal property analyser with a unique assertion coverage evaluator eliminates the guesswork from quality assertion generation.

OneSpin Solutions 360 EC-FPGA
Functional equivalence checking / FPGA / FV / SAFETY

360 EC-FPGA ensures systematic errors are not introduced in the RTL implementation process of programmable devices.

Sigasi Studio
VHDL code editing, browsing & checking / FPGA / SAFETY / ASIC

The Sigasi Studio platform was developed specifically to make HDL design easier and more efficient. It is based on the Eclipse platform and brings the same kind of real-time code checking assistance that software engineers have enjoyed for years firmly into the hardware arena.