FPGAs have come an incredibly long way since their introduction in the mid-1980s. While low gate-count devices are still used extensively at one end of the spectrum we now have broad availability of multi-million gate FPGAs with embedded processor cores. Accordingly, the automation of design and verification tasks is essential if projects are to be completed on time and, importantly, with confidence.
Active-HDL is a Windows-based, integrated design creation and simulation solution for engineers working on projects ranging from simple PLD ‘glue logic’ all the way up to several-million-gate system-on-chip FPGAs.
ALINT-PRO is a design rule checking (DRC) tool. It uses rule files (‘policies’) to check that a design’s RTL adheres to a defined RTL coding style. It decreases development time dramatically by identifying design issues early in the development schedule.
Riviera-PRO addresses the verification requirements of engineers targeting large gate-count FPGAs, ASICs and System-on-Chip devices. It gives engineers the ultimate testbench in terms of productivity, reusability and automation; all by combining a high-performance simulation engine with advanced debugging capabilities (at different levels of abstraction).
Aldec and Microsemi have joined forces to offer an innovative, reprogrammable prototyping solution for Microsemi RTAX-S/SL, RTAX-DSP and RTSX-SU space-fight system designs. Unlike the traditional One Time Programmable (OTP) anti-fuse space-qualified FPGAs, the Aldec prototype adaptor uses flash-based, Microsemi ProASIC 3E FPGA technology for design prototype re-programmability.
The Sigasi Studio platform was developed specifically to make HDL design easier and more efficient. It is based on the Eclipse platform and brings the same kind of real-time code checking assistance that software engineers have enjoyed for years firmly into the hardware arena.