Advanced VHDL Testbenches & Verification

13-24 September - Online, Live and Interactive

Advanced VHDL Testbenches & Verification

Learn the latest VHDL Verification methodologies, with IEEE VHDL working group chair Jim Lewis

Blog: OSVVM, a VHDL verification methodology that is easy to adopt

By Nomita Goswami, FirstEDA

Blog: OSVVM, a VHDL verification methodology that is easy to adopt

Aldec Riviera-PRO 2020.10 Released

Aldec Riviera-PRO 2020.10 Released

The new Riviera-PRO 2020.10 now supports OSVVM 2020.08 and has enhanced language support and new debugging features aim to boost productivity

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