Riviera-PRO  Riviera-PRO Icon 32

ADVANCED VERIFICATION PLATFORM / FPGA / FV / ASIC

Riviera-PRO addresses the verification requirements of engineers targeting large gate-count FPGAs, ASICs and System-on-Chip devices. It gives engineers the ultimate testbench in terms of productivity, reusability and automation; all by combining a high-performance simulation engine with advanced debugging capabilities (at different levels of abstraction).

Riviera-PRO is a high performance, high capacity, multi-language simulator that provides a unified debug environment for VHDL, Verilog, SystemVerilog, SystemC and PSL. The core simulation engine includes advanced simulation optimisation for both VHDL & Verilog simulation.

As well as supporting traditional HDL verification techniques, Riviera-PRO provides advanced analysis and debug capabilities for UVM and TLM verification methodologies.

Riviera-PRO provides project and workspace capability as well as script-based operation for compilation and simulation.

Riviera-PRO is an extremely capable EDA solution, with all the features that you would expect to see on a high-end verification tool.

Features and Benefits

icons8-facebook-like-64 High Performance Simulation

  • Extensive simulation optimisation algorithms to achieve the highest performance in VHDL, Verilog/SystemVerilog, SystemC, and mixed-language simulations
  • Industry-leading capacity and simulation performance enable high regression throughput for developing the most complex systems
  • Complete support for the latest Verification Libraries, including Universal Verification Methodology (UVM) and Open Source VHDL Verification Methodology (OSVVM)

 
icons8-search-more-48 Advanced Debugging

  • Integrated multi-language debug environment allows the automating of time-consuming design analysis tasks and fixing bugs quickly
  • UVM Toolbox, UVM graph, Class Viewer, Transaction streams and data to allow visual mapping and debugging of designs based on OVM/UVM class libraries
  • Built-in debugging tools provide code tracing, waveform, dataflow, FSM window, coverage, assertion, and memory visualisation capabilities
  • Comprehensive Assertion-Based Verification (SVA and PSL) for increased design observability and decreased debug time
  • Advanced Code and Functional Coverage capabilities and Coverage analysis tools for fast metric-based verification closure
  • Efficient verification flow with user-defined test plan linking with coverage database
  • Plot viewer and Image viewer tools for visual representation of large arrays of data
icons8-money-50 Industry’s Best ROI

  • Riviera-PRO enables Aldec customers to deliver innovative products at a lower cost in a shorter time
  • Features partnerships and integrations necessary to build complete design and verification flows
  • Deployment of any Aldec solution is accompanied by comprehensive training and industry-leading support
FirstEDA is extremely familiar with Riviera-PRO. We have considerable hands-on experience having supported users – verifying FPGA, ASIC and SoC designs – for several years. Working with our customers we have experience of deploying Riviera-PRO on leading-edge FPGA programmes, using advance VHDL techniques such as OSVVM functional coverage and SystemVerilog UVM constrained random tests.

Related Articles, Blogs and Videos

VIDEO: Riviera-PRO 1.2 Basics: HDL Editor and Templates

VIDEO: Riviera-PRO 1.7 Basics: Coverage Overview

VIDEO: Riviera-PRO 1.9 Basics: Testbench Creation

VIDEO: Riviera-PRO 2.7 Advanced: UVM Toolbox

VIDEO: Riviera-PRO 3.3 Interfacing: QEMU Co-Simulation with Riviera-PRO

BLOG: Do I Really Need A Commercial Simulator?

BLOG: Trace Your Assertions

BLOG: Unit Linting: An Easy Way To Prevent Code Review Issues

ARTICLE: Visible Benefits

ARTICLE: View From Above

RELEASE: Aldec Enhances Riviera-PRO’s VHDL and UVVM Support

RELEASE: Riviera-PRO Users To Benefit From Automatic UVM Register Generation Plus The Latest Verification Methodology Libraries

 

 

Ian Gibbins Ian Gibbins, Applications Specialist, FirstEDA

“With increasing FPGA complexity comes the demand for high performance simulation and verification tools. Our users tell us that Riviera-PRO meets this complexity demand, with extensive language support including VHDL-2018, support for the latest verification libraries (including OSVVM and UVM) and advanced debugging tools. In addition they are finding that the extensive coverage capabilities for fast metric-based verification closure, scripting and batch processing along with the high performance common kernel simulation engine, is providing a solution to meet their performance and verification needs.”

Contact us for more information and pricing.