Running an ASIC or SoC design on an FPGA prototype is a reliable way to ensure that it is functionally correct. We offer various FPGA Prototyping solutions and provide on-site support and consulting, to enable rapid deployment of these solutions.

FPGAs continue to grow in both capability and capacity, and now incorporate microprocessors, DSPs, application specific IP, programmable fabric and high performance interfaces. FPGA-based prototyping is the method to prototype SoC and ASIC designs on FPGA, for the purpose of hardware verification and early software development.

Hardware Assisted Verification / HW-V / PROTO / ASIC

HES-DVM is a fully automated verification and validation system for SoC ASIC designs of 200M+ ASIC gates. Aldec’s FPGA Hardware Emulation Solution is based on the latest Xilinx Virtex-7 devices and is capable of simulation acceleration, and SCE-MI transaction co-emulation.

Aldec HES-7
ASIC Prototyping / HW-V / PROTO / ASIC

HES-7 provides SoC and ASIC verification and validation teams with a scalable and high-quality FPGA-based ASIC prototyping solution. Each HES-7 board with dual Xilinx Virtex-7 2000T has 4million FPGA logic cells (or up to 24million ASIC gates of capacity) not including the DSP and memory resources.

Prototyping Microsemi Rad Tolerant Devices / FPGA / PROTO

Aldec and Microsemi have joined forces to offer an innovative, reprogrammable prototyping solution for Microsemi RTAX-S/SL, RTAX-DSP and RTSX-SU space-fight system designs. Unlike the traditional One Time Programmable (OTP) anti-fuse space-qualified FPGAs, the Aldec prototype adaptor uses flash-based, Microsemi ProASIC 3E FPGA technology for design prototype re-programmability.