IDesignSpec helps IP/SoC Design architects and engineers to create an executable specification for registers and automatically generate output for Software and Hardware teams.


The exceptional innovation comes with an intuitive tool flow as the specifications can be written in MS Word, MS Excel, LibreOffice or text-based industry standard formats such as SystemRDL, RALF or IP-XACT. IDesignSpec captures simple as well as special registers, signals, interrupts, and generates synthesisable RTL, UVM model, C/C++ Headers, HTML and PDF.


IDesignSpec is an end-to-end solution for design and verification of all SoC addressable registers and interrupts, enabling design, verification, firmware and tech pub teams to collaborate from a single specification.

  • Describe registers in Word, Excel, Calc, SystemRDL, IP-XACT, CSV or YAML
  • Auto-generate sign-off quality register RTL code, UVM models, C/C++ headers and documentation
  • Supports various standard bus: AXI4, AXI-Lite, AHB, APB, Wishbone or proprietary

IDesignSpec is a great tool that bridges the gap of register specifications to the design and verification of the actual logic.

Features and Benefits

icons8-facebook-like-64 Automatically verify all addressable registers in the design to ensure generated register code is correct
icons8-synchronize-filled-50 Create synthesisable code for registers for design teams and keep them synchronised with requirements


Faster and more accurate Device Driver, Firmware and application software development eliminates errors in communication of interfaces between functional teams


Imports : IP-xact, SystemRDL, XML, CSV, register data stored in native editor format. Provides complete register data portability with design teams and customers
icons8-documents-50 Automatically create product documentation for customers and technical publications
icons8-finish-flag-48 Improves productivity of engineers and quality of results
icons8-business-group-80 Supports Architecture, Design, Verification, Diagnostics, Firmware, Application Software and Documentation teams
icons8-delivered-box-64 Extensible: User defined transformations using Tcl or XSLT

Register Design Entry
Equipped with user-friendly templates, you can specify your registers using any of the add-ins to Word, Excel, OpenOffice Calc or FrameMaker. Built with high-performance IP-XACT compiler and SystemRDL compiler, simple and complex registers can be created hierarchically such that large SoC designs are divided into manageable sub-blocks that are represented symbolically, designed and connected together. This methodology enables you to work on different parts of the design in parallel with a large team. Users are able to convert register spec from IP-XACT to UVM or from SystemRDL to IP-XACT.

Code Generation
Based on the golden specification, various SoC teams can use the high-performance code generators via GUI or command line. The generated RTL Code (VHDL, Verilog, SystemVerilog or SystemC) for the registers is human-readable with easy-to-follow comments. The RTL also includes a bus slave and a decode logic specific to the bus protocol (AHB, APB, AXI, AXI-Lite, or proprietary), ensuring instant connection of the application logic to the register bus. The UVM Register Model Generater generates UVM verification model with Register Arrays, Memories, Indirect Access Registers, FIFO Registers and Coverage, Constraints Models and hdl_path. Users are able to customise various outputs by using our popular Velocity Template and TCL API, enabling you to meet various requirements for RTL, C++ Classes, verification code and documentation.

Special Registers
The UVM library includes examples of few commonly used special registers such as Indirect, Indexed, Alias and RO/WO Registers. But today’s SoCs demand more specialised register behaviour to meet various HW/SW interface requirements. IDesignSpec supports over 20 special registers including Shadow, Lock, Trigger-Buffer, Interrupt, Counter or External.

Document Generation
The customisable Document Generator can output file formats such as HTML, PDF, Custom PDF, .doc, .xls, DITA, IP-XACT, SystemRDL or ARM CMSIS.


Advanced UVM Code Generator with SystemRDL to IP-XACT and IP-XACT to UVM Functionalities

What is IP-XACT?

An Accellera standard that provides EDA vendors, IP providers, and SoC design communities with a well-defined and unified specification for the meta-data that represents the components and designs within an electronic system. IDesignSpec includes an IP-XACT Compiler that is able to parse IP-XACT files and output RTL, C Headers and documentation, and supports IP-XACT to UVM verification model conversion.

What is SystemRDL?

Another Accellera standard that supports the full project cycle of registers from the specification, model generation, and design verification to maintenance and documentation. SystemRDL minimises the problems encountered in describing and managing registers. IDesignSpec includes a SystemRDL Compiler that is able to parse SystemRDL files and output RTL, C Headers and documentation, and supports SystemRDL to IP-XACT conversion.

IDesignSpec Availability

IDesignSpec is available as s a plug-in for popular editors that are commonly used to document registers (Microsoft Word, Microsoft Excel) and as a command line utility for Windows, Linux and Solaris platforms. IDesignSpec has three licensing options, Node Locked, Floating Network License and WAN licensing.

Advanced UVM Code Generator

Based on the register definition in IP-XACT or SystemRDL (also Word, Excel or YAML), the UVM Code Generator is able to generate a comprehensive UVM register model with an instance of a register block, files, arrays and memories. Users are also able to define the required coverage type for fields, bits and address-map, and the UVM code generator is able to generate the coverage code for all the components inside the top level block. Customising the code is simple to do by using several UVM properties such as hdl_path, uvm_add_regmap, uvm_backdoor/frontdoor – the UVM code generator will generate the UVM code based on the properties.


Related Articles, Blogs and Videos

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BLOG: RISC-V TileLink Bus Protocol Support in IDesignSpec

BLOG: Creating Test Sequences for RISC-V Cores and SoCs

ARTICLE: IDEX Biometrics Selects Agnisys IDesignSpec to Aid Development of the Next-Generation ASICs for IoT Security

VIDEO: IDesignSpec: Executable Register Specification

VIDEO: Verifying Registers using UVM and IDesignSpec



  David Clift, Applications Specialist, FirstEDA

“It is vitally important that design teams have a consistent methodology for managing the register map data of their designs. iDesignSpec allows design teams to have a central definition of the memory map of their design, be this in Microsoft Word or Excel format, or industry standard formats such as SystemRDL or IP-XACT. Once this is validated by the tool, they can generate consistent HDL code, documentation, C/C++ headers and more.”

Contact us for more information and pricing.