HES-DVM  HES Icon 32

HARDWARE ASSISTED VERIFICATION / HW-V / PROTO / ASIC

HES-DVM is Aldec’s fully automated verification and validation system for SoC and ASIC designs of 600M+ gates. This Hardware Emulation Solution is based on the latest Xilinx Virtex-7 and UltraScale devices and is capable of simulation acceleration, and SCE-MI transaction co-emulation.

RTL Debug

HES-DVM provides full control of the system in both acceleration and co-emulation with SCE-MI. As well as control, HES-DVM provides 100% design visibility and with Aldec’s HVD technology the impact on system performance can be minimised. HES-DVM also includes Aldec’s SyntHESer high-speed HDL synthesizer, which performs 10x faster than a leading standalone synthesis tool.

Debug Capabilities

  • High performance debug infrastructure (HMDB bus)
  • Flexible static probes, advanced embedded logic analyser for at-speed RTL debug
  • Dynamic debugging with HVD technology
  • Emulation triggering and control capabilities
  • Memory viewer and write access tools including API

Hybrid Virtual Prototyping

Utilising virtual platforms with HES-DVM’s co-emulation interface, developers are able to connect SystemC TLM 2.0 modules to their hardware DUT via high speed transactors. HES-DVM memory management API enables developers to load applications to program memory, decreasing overall system boot-time.

HES A Scalable System

The use of Xilinx devices is a cost-effective solution for hardware emulation and enables replication of the system for software development and verification regression systems. Aldec supports customer FPGA systems as part of its custom board support.

Time To Emulation / TTE

The use of Xilinx devices is a cost-effective solution for hardware emulation and enables replication of the system for software development and verification regression systems. Aldec supports customer FPGA systems as part of its custom board support.

 

The Design Verification Manager (DVM) environment enables system ‘bring-up’ times of weeks, as opposed to months. This allows earlier hardware and software integration in the project schedule, resulting in reduced development time and a shorter time to market.

HES-DVM is used by semiconductor companies developing complex SoC ASICs as well as IP providers. Typically used in combination with simulation and traditional hardware accelerators, FPGA base systems provide unmatched scalability and performance.

 

Related Articles, Blogs and Videos

VIDEO: SCE-MI 2 Emulation

WEBINAR: 100% Signal Visibility during Emulation Dynamic Debug with HVD Technology

WEBINAR: Aiding ASIC Design Partitioning for multi-FPGA Prototyping

WEBINAR: HW / SW Co-Verification: Why wait for silicon?

WEBINAR: New Mirror-Box Technology for Hardware-Assisted Simulation

RELEASE: Aldec shortens time of ASIC design prototype bring-up in FPGA with HES-DVM Proto mode

ARTICLE: HES-DVM Offers Enhanced Automation in FPGA Prototyping

RELEASE: Aldec cuts ASIC design prototype bring-up time with HES-DVM’s automatic partitioning tool and faster HDL-to-FPGA compilation times

 

David Clift David Clift, Applications Specialist, FirstEDA

“When deploying today’s complex ASIC and SoC designs, efficient verification solutions are required, Aldec’s Design Verification Manager (DVM) is a fully scalable verification environment supporting bit-level acceleration, emulation and prototyping. Historically multi-FPGA design setup issues like partitioning, multiplexing limited I/O interconnections and mapping multiple clock domains across multiple devices may cause significant delays in prototype bring-up and verification schedule, but with HES DVM and its automated partitioning tool design setup is reduced from weeks to days.”

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