Article: Verification Planning And Management With Formal
Getting a unified look at what formal, simulation, and acceleration/emulation contribute to verification....
30 January, 2020
Archive
Article: Evaluating NVMe SSD Multi-Gigabit Performance
Using an embedded prototyping board to reduce system bring-up time and simplify customisation efforts....
30 January, 2020
Article: Making Sure RISC-V Designs Work As Expected
Open-source growth predictions are impressive, but the verification process can be harder than with commercial ISAs....
30 January, 2020
Release: Cobham Gaisler successfully verifies its first RISC-V processor, NOEL-V, using Aldec’s Riviera-PRO for HDL Simulation
Aldec today announced that Cobham Gaisler has successfully verified its first RISC-V line of processors, called NOEL-V, using Riviera-PRO for mixed-HDL simulation....
28 January, 2020
Article: Securing Chips from the Ground Up
Pre-silicon validation and verification of hardware security requirements are crucial, which pushes the need for more robust, efficient design flows....
23 January, 2020
Article: Uses And Limitations Of AI In Chip Design
OneSpin’s CEO explains what’s changing in AI, where it’s being used, and what still has to be fixed....
15 January, 2020
Article: Auto Industry Shifts Gears On Where Data Gets Processed
How to manage massive amounts of data in real time still isn’t clear, but it can’t be done in the cloud....
09 January, 2020
Article: Open Source Hardware Risks
There’s still much work to be done to enable an open source hardware ecosystem....
09 January, 2020
Article: Agnisys – Field Error Signal
To enable the user to debug easily, and incorporate this functionality in RTL, IDesignSpec (IDS) generates the required error signals....
02 January, 2020
Article: Improving Algorithms With High-Level Synthesis
New directions for a commonly used technology....
02 January, 2020