Article: Agnisys - Field Error Signal - FirstEDA
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Article: Agnisys – Field Error Signal

By: Chaturvedi Purushotam Kumar, R&D Engineer


Error signals are part of the communication between a processor and an IP and play a vital role during design and verification stages. They enable the processor to be kept informed about any invalid access of a register/field, which may further result in transaction failure.


From a verification perspective, in UVM, an error is automatically generated when we try to write into a read only register/field or read from a write only register/field. However, no such intimation of the invalid transaction is given to the user through RTL, as a result of which user has to spend a considerable amount of time to debug the reason behind invalid transactions. To enable the user to debug easily, and incorporate this functionality in RTL, IDesignSpec (IDS) generates the required error signals. In the case of RTL, IDS generate read and write errors for both registers and fields based on their software access.


As an example, consider a register with a single field. The software access of that field is basically the software access of the entire register. If the field is read only, then a write error will be generated for the entire register, rather than an individual field, whenever the processor attempts a write transaction on this read only register. Similarly, read errors are generated whenever the processor performs read transactions on a write only register.


If the register has a multiple number of fields with each having different software access (ro/wo), then IDesignSpec automatically generates an error signal at a field level if an invalid transaction is attempted on it.