Article: Making Sure RISC-V Designs Work As Expected - FirstEDA
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Article: Making Sure RISC-V Designs Work As Expected

January 30th, 2020 – By: Ann Steffora Mutschler



Open-source growth predictions are impressive, but the verification process can be harder than with commercial ISAs.


The RISC-V instruction set architecture is attracting attention across a wide swath of markets, but making sure these devices work as expected is proving as hard, if not harder, than other commercially available ISAs.


The general consensus is that open source lacks the safety net of commercially available IP and tools. Characterisation tends to be generalised, rather than specific for a particular application, and open-source tools are more difficult to work with and frequently less reliable. This has created a market for commercial implementations of both the RISC-V ISA, as well as tools aimed specifically for RISC-V, but it also has opened the door for commercially developed tools and IP that simplify and add consistency to RISC-V implementations.


All of this is happening amid rapid growth throughout the RISC-V ecosystem. Semico Research predicts the communications segment will achieve a 209% compound annual growth rate by 2025, and that RISC-V will capture more than 6% of the CPU core business in that market between now and 2025. The firm also forecasts the available market for automotive will have a CAGR of 160% during that period, and the total available market for 5G infrastructure will reach 19 million units by 2025, with RISC-V playing an important role in both markets. In total, RISC-V growth is forecast to increase 160% during that period in devices targeted at a broad range of performance levels.