Release: Cobham Gaisler successfully verifies its first RISC-V processor, NOEL-V, using Aldec’s Riviera-PRO for HDL Simulation - FirstEDA
23171
portfolio_page-template-default,single,single-portfolio_page,postid-23171,ajax_fade,page_not_loaded,,qode-child-theme-ver-1.0.0,qode-theme-ver-14.5,qode-theme-bridge,wpb-js-composer js-comp-ver-6.1,vc_responsive

Release: Cobham Gaisler successfully verifies its first RISC-V processor, NOEL-V, using Aldec’s Riviera-PRO for HDL Simulation

January 28th, 2020

 

 

Henderson NV, USA – Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that Cobham Gaisler has successfully verified its first RISC-V line of processors, called NOEL-V, using Riviera-PRO for mixed-HDL simulation.

 

NOEL-V is a synthesisable VHDL model of a 64-bit processor that implements the RISC-V architecture, with an advanced 7-stage dual-issue in-order pipeline and provides up to 4.69 CoreMark/MHz. “As a leading vendor of space-grade microprocessors, we needed to verify NOEL-V using a reliable and high-performance RTL simulator with advanced debugging and DRC checking capabilities”, said Jan Andersson, Director of Engineering at Cobham Gaisler. “We used Riviera-PRO for functional, gate-level and timing simulation and we were very pleased with its rich VHDL support, compile and simulation speed.”

 

“Because of its open-source model, RISC-V is a game-changing technology for hardware that spans across various embedded applications including space and mission-critical”, said Louie De Luna, Director of Marketing at Aldec. “We’re excited to help and work with Cobham Gaisler, and we look forward to solving new verification challenges for the future generations of NOEL-V.”