Article: Improving Algorithms With High-Level Synthesis - FirstEDA
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Article: Improving Algorithms With High-Level Synthesis

December 30th, 2019: By – Ann Steffora Mutschler

 

 

New directions for a commonly used technology.

 

Most computer algorithms today are developed in high-level languages on general-purpose computers. But someday they may be deployed in embedded systems where the development, verification, and validation of algorithms is done in languages like python, Java, C++, or even numerical frameworks like MatLab.

 

This is the goal of high-level synthesis (HLS), and it aims to solve a fundamental problem in system design today. The basic idea is allowing hardware designers to build and verify hardware, with better control over optimisation of the design architecture, describing the design at a higher level of abstraction while the tool implements the RTL. It also may be possible to use HLS to improve today’s algorithms that run on that hardware.

 

The ultimate description will be in a hardware description language (HDL) at the register transfer level (RTL). So it’s not so much the algorithm that will be affected by HLS. It’s the implementation of the algorithm.