Article: Automated connectivity checking with formal verification
Given a sufficiently robust set of properties to describe intended behaviour, formal tools can not only find all bugs but also prove that there are...
26 September, 2019
Archive
Article: High-Level Design And High-Level Verification
Expectations for C++/SystemC designs must be set properly. ...
26 September, 2019
Article: The Growing Impact Of Portable Stimulus
Experts at the Table: How the Portable Test and Stimulus Standard has affected the industry and who are the early adopters? ...
26 September, 2019
Release: Aldec cuts ASIC design prototype bring-up time with HES-DVM’s automatic partitioning tool and faster HDL-to-FPGA compilation times
The 2019.09 release of HES-DVM provides fast compilation and FPGA partitioning automation, aiding greatly in design setup for physical prototyping on multi-FPGA boards from Aldec...
24 September, 2019
Sigasi Studio v4.5 Released
Sigasi Studio 4.5 release, where Sigasi Studio’s editor became a lot faster, as in up to 3 times faster. We also added HTML documentation, and...
20 September, 2019
Article: FPGA Design Tradeoffs Getting Tougher
As chips grow in size, optimizing performance and power requires a bunch of new options and methodology changes. ...
16 September, 2019
Release: SoC & ASIC designers to benefit greatly from multiple HES Proto-AXI enhancements
The enhancements include support for QEMU and SystemC TLM version 2.0, plus resources that increase the interoperability of HES Proto-AXI with third party tools ...
10 September, 2019
Event: FPGA World 2019
FirstEDA's training partner, chair of the IEEE VHDL Working Group and OSVVM architect, Jim Lewis is presenting at this year’s FPGA World conference. ...
04 September, 2019
Article: IP’s Growing Impact On Yield And Reliability
Managing IP quality and compatibility is becoming more difficult at advanced nodes and in safety-critical markets. ...
04 September, 2019
Article: RISC-V EMEA Roadshow Spotlight: OneSpin Solutions
OneSpin Solutions is one of the featured RISC-V Foundation members in the EMEA roadshow, presenting the session, “Verifying the Full Scope of RISC-V Integrity.” ...
27 August, 2019