Release: Aldec cuts ASIC design prototype bring-up time with HES-DVM’s automatic partitioning tool and faster HDL-to-FPGA compilation times - FirstEDA
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Release: Aldec cuts ASIC design prototype bring-up time with HES-DVM’s automatic partitioning tool and faster HDL-to-FPGA compilation times

Date: Sep 24, 2019

 

The 2019.09 release of HES-DVM provides fast compilation and FPGA partitioning automation, aiding greatly in design setup for physical prototyping on multi-FPGA boards from Aldec and some third-party boards

 

Henderson, NV, USA – September 24, 2019 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced automatic FPGA partitioning to its popular HES-DVM; the company’s fully automated and scalable hybrid verification environment for SoC and ASIC designs.

 

Traditionally, and subject to design complexity and constraints, the manual partitioning of multiple FPGAs used for prototyping can take days, or even weeks, whereas the automation in HES-DVM can perform the task in minutes; ideal for exploratory, What-If scenarios.

 

The latest release of HES-DVM, 2019.09, also features Aldec’s proprietary HDL compiler. Called SyntHESer, and announced earlier this year, in a recent in-house bench test, the compiler performed 10x faster than a leading standalone synthesis tool, when handling identical blocks of HDL for a circa 45-million-gate Deep Learning Accelerator (DLA) design.

 

“These additions to HES-DVM rise to some of the biggest challenges associated with the FPGA-based prototyping of an ASIC design,” said Zibi Zalewski, General Manager of Aldec’s Hardware Division. “With the 2019.09 release of HES-DVM, the most tedious and challenging activities, such as creating and matching partitions with on-board FPGAs or assigning limited FPGA I/O resources, are fully automated.”