Article: RISC-V EMEA Roadshow Spotlight: OneSpin Solutions - FirstEDA
portfolio_page-template-default,single,single-portfolio_page,postid-23069,ajax_fade,page_not_loaded,,qode-child-theme-ver-1.0.0,qode-theme-ver-14.5,qode-theme-bridge,wpb-js-composer js-comp-ver-6.1,vc_responsive

Article: RISC-V EMEA Roadshow Spotlight: OneSpin Solutions

August 21, 2019


OneSpin Solutions is one of the featured RISC-V Foundation members in the EMEA roadshow, presenting the session, “Verifying the Full Scope of RISC-V Integrity.” OneSpin offers a range of EDA solutions for digital integrated circuits, which enables users to address design challenges in areas where reliability really counts: safety-critical verification, SystemC/C++ high-level synthesis (HLS) code analysis and FPGA equivalence checking. Read on to learn more about the company and what it will be showcasing at the events.


What applications or problems does your company’s technology solve for engineers?

  • OneSpin allows RISC-V processor core developers to fully verify their designs to assure integrity at all levels from functional correctness, safety, security and trust. This is essential as RISC-V developers must compete with more established processors in the market as well as other RISC-V processors. To stand out against the many available options, RISC-V processor core developers must thoroughly verify their designs. This requirement goes beyond Instruction Set Architecture (ISA) compliance checking to include optional ISA features, custom extensions and microarchitectural implementation choices.RISC-V system-on-chip (SoC) designers must be able to confirm the integrity of the RISC-V cores they integrate, including proof that no Trojans or hardware vulnerabilities lurk in the design, and verify that the cores are integrated properly into SoCs. Safety-critical applications with strict standards add even more verification requirements.