September 4th, 2019 – By: Ann Steffora Mutschler
Managing IP quality and compatibility is becoming more difficult at advanced nodes and in safety-critical markets.
Chipmakers are finding it increasingly difficult to achieve first-pass silicon with design IP sourced internally from different IP providers, and especially with configurable IP.
Utilising poorly qualified IP and waiting for issues to appear during the design-to-verification phase just before tape-out can pose high risks for design houses and foundries alike in terms of cost and time to market. But managing the IP quality can assume different dimensions from simulations, DRC-LVS, IP traceability, conformance to standards, and configuration checks based on available formats. These issues are well understood, but as the amount of third-party IP in designs has grown, so have the number of potential interactions. As a result, quality has escalated to a critical status.