Article: FPGA Design Tradeoffs Getting Tougher - FirstEDA
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Article: FPGA Design Tradeoffs Getting Tougher

September 16th, 2019 – By: Ann Steffora Mutschler

 

 

As chips grow in size, optimising performance and power requires a bunch of new options and methodology changes.

 

FPGAs are getting larger, more complex, and significantly harder to verify and debug.

 

In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the cost and time of developing an ASIC. But today, both FPGAs and eFPGAs are being used in the most demanding applications, including cloud computing, AI, machine learning, and deep learning. In some cases, they are being combined with an ASIC or some other type of application-specific processor or accelerator inside a chip, a package or a system. As a result, requirements for effective power, performance, and area (PPA) are every bit as strict as for ASICs and full-custom chips, and the tradeoffs are equally complicated and often intertwined.

 

“For SoCs with an FPGA, there are several approaches,” said Stuart Clubb, product marketing manager at Mentor, a Siemens Business. “There’s the ASIC team that is building an SoC and adding an embedded FPGA into the fabric for something that’s programmable — invariably hanging off of a bus and used as some kind of programmable accelerator that they don’t quite know what they’re going to do with yet, or which may be changed. For them, the rigors of the ASIC flow are more commonly adopted.”