The 2019.09 release of HES-DVM provides fast compilation and FPGA partitioning automation, aiding greatly in design setup for physical prototyping on multi-FPGA boards from Aldec...
Sigasi Studio 4.5 release, where Sigasi Studio’s editor became a lot faster, as in up to 3 times faster. We also added HTML documentation, and...
As chips grow in size, optimizing performance and power requires a bunch of new options and methodology changes. ...
The enhancements include support for QEMU and SystemC TLM version 2.0, plus resources that increase the interoperability of HES Proto-AXI with third party tools ...
FirstEDA's training partner, chair of the IEEE VHDL Working Group and OSVVM architect, Jim Lewis is presenting at this year’s FPGA World conference. ...
Managing IP quality and compatibility is becoming more difficult at advanced nodes and in safety-critical markets. ...
OneSpin Solutions is one of the featured RISC-V Foundation members in the EMEA roadshow, presenting the session, “Verifying the Full Scope of RISC-V Integrity.” ...
SystemVerilog assertions can nicely capture many hardware requirements. However, more is needed for security verification. ...
Can a software engineer create hardware? It may be possible but not in the way that existing high-level synthesis tools do it. ...
This paper presents the OneSpin RISC-V Integrity Verification Solution and discussed how its components verify all four aspects of design integrity at both the processor...