Article: Open Source Hardware Risks
There’s still much work to be done to enable an open source hardware ecosystem....
09 January, 2020
Archive
Article: Agnisys – Field Error Signal
To enable the user to debug easily, and incorporate this functionality in RTL, IDesignSpec (IDS) generates the required error signals....
02 January, 2020
Article: Improving Algorithms With High-Level Synthesis
New directions for a commonly used technology....
02 January, 2020
Article: Agnisys – Board Prototyping
Given the importance of board prototyping, ISequenceSpec (ISS) from Agnisys provides a solution to automatically generate sequences for boards....
01 January, 2020
Article: Crossed Wires On Domains
How well understood are domain crossings, especially when it involves multiple domains? They require a combination of methodology and tools....
20 December, 2019
Article: Will Open-Source Processors Cause A Verification Shift?
Tools and methodologies exist, but who will actually do the verification is unclear....
20 December, 2019
Article: What Worked, What didn’t In 2019
The year started out shaky, but EDA racked up solid growth and semiconductors show good promise for 2020....
20 December, 2019
Blog: An Introduction to Assertion-Based Verification – Part 1
Part 1 explains what an assertion is, talks about the languages and develops the basic terms and ideas....
19 December, 2019
Release: Aldec Enhances Riviera-PRO’s VHDL and UVVM Support
Aldec has added features to its Riviera-PRO functional verification platform that provide further support when working with the latest version of VHDL (2018) as well...
18 December, 2019
Press Release: Inaugural OneSpin Osmosis User Conference Delivers Quality Content, Deep Verification Insights
OneSpin is pleased to announce the success of the company’s inaugural users conference, Osmosis. ...
16 December, 2019