Welcome Back to DAC – in Person – in San Francisco
Agnisys Delivers Fully Automated, Specification-Based Design and Verification Flow for Registers and Sequences...
02 December, 2021
Archive
Productivity Through Methodology: Aldec Adds UVM Generator in Riviera-PRO 2021.10
Productivity Through Methodology: Aldec Adds UVM Generator to Riviera-PRO, Plus Updates Its OSVVM and UVVM Libraries...
17 November, 2021
FirstEDA Newsletter – October 2021
FirstEDA Newsletter - October 2021 - Training update, DVCon Europe, blogs, webinars and more...
05 November, 2021
An Update on Functional Safety and ISO 26262
An Update on Functional Safety and ISO 26262 from Agnisys...
05 November, 2021
Blog: Agnisys – A Hardware Engineer’s Perspective
Agnisys IDS creates a centralised Executable Register Specification & automatically generates Synthesisable Models, C headers, UVM Models & testbenches...
02 February, 2021
Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs
Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs...
17 November, 2020
Specification-Driven UVM Testbench Generation
Specification-Driven UVM Testbench Generation...
23 September, 2020
Sigasi Studio 4.9 latest Release Notes
Sigasi Studio 4.9 latest Release Notes ...
23 September, 2020
6 Minutes of Security: Cybersecurity Risks in Automotive Electronics
6 Minutes of Security: Cybersecurity Risks in Automotive Electronics...
17 September, 2020
UVM-based Verification of Custom Instructions with RISC-V Cores
UVM-based Verification of Custom Instructions with RISC-V Cores...
17 September, 2020