UVM-based Verification of Custom Instructions with RISC-V Cores - FirstEDA
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UVM-based Verification of Custom Instructions with RISC-V Cores

By integrating Aldec’s Riviera-PRO with Codasip’s Studio, verification of RISC-V CPU custom instructions at the RTL implementation level becomes an incredibly powerful platform for RISC-V processor deployment.

 

In this presentation, we will show in Studio, how users can describe the RISC-V architecture and add custom instructions using CodAL high level language, modify the pipeline, configure random instruction generator, auto-generate the HDK, SDK, RTL implementation and C++ reference model and UVM environment, start RTL simulation, setup breakpoints and debug.

 

We will then show in Riviera-PRO, how users can run RTL simulation and debug applications and core architecture, inspect simulation waveforms, use the UVM Graph & Toolbox to view the graphical representation of the UVM components, objects and the transaction level modeling (TLM) connections between them, giving the user an overall perspective of the testbench architecture and the dataflow. We will also show how you can collect and analyze both functional coverage and code coverage.