Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs - FirstEDA
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Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

The latest release of HES-DVM provides a simulation acceleration flow, providing significant RTL simulation speed-up of designs targeting Microchip FPGA devices.

 

Henderson, NV, USA – November 3, 2020 – Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM simulation acceleration flow for Microchip’s Polarfire, SmartFusion2 and RTSX/RTAX FPGA designs using Aldec’s HES-MPF500-M2S150 prototyping board.

 

“Aldec has a long history of developing hardware assisted verification solutions, with our first HES board and simulation acceleration platform released 20 years ago,” said Zibi Zalewski, General Manager of Aldec’s Hardware Division. “We also have a proven track record of developing Microsemi/Microchip FPGA prototyping boards, and it is great that we can combine these areas of expertise to meet today’s verification challenges.”