Specification-Driven UVM Testbench Generation - FirstEDA
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Specification-Driven UVM Testbench Generation

In February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM). It’s no exaggeration to say that UVM changed the world of semiconductor verification. It wasn’t the first verification methodology, and not even the first to use SystemVerilog, but it was developed and supported by all major electronic design automation (EDA) vendors. Users could write testbenches using the UVM building-block library and its detailed guidelines, secure in the knowledge that simulators and other tools would handle them properly.


UVM focused the diverse set of constructs and powerful capabilities available in SystemVerilog on the specific task of building a reusable verification environment. Object-oriented programming (OOP) support meant that users could extend the building blocks without modifying them. Adherence to the guidelines made verification components reusable “horizontally” across projects and even across companies. Passive components such as monitors and coverage collectors, and even some active interface models, could be reused “vertically” from block to subsystem to system.


Above all, UVM brought automation to testbenches. Verification engineers no longer had to hand-write tests for every feature in the design. They could set up an environment in which sequencers automatically generated an unlimited number of tests, of any length, with countless variations. Chip verification teams today still enjoy these benefits, but they are not without cost. It takes time and a fair amount of expertise to set up a UVM environment. Since it eliminates a huge amount of manual testing and provides better verification coverage, the up-front investment is clearly worth it.