Insight: Exploring An Open Source Risc-V Core
Western Digital published the (System)Verilog sources of their Open Source Risc-V core on GitHub. Of course I wanted to try how easy it was to...
26 February, 2019
Archive
Article: OneSpin Launches First Formal RISC-V Integrity Verification Solution
OneSpin unleashed its RISC-V Integrity Verification Solution for development and assessment of RISC-V cores, leveraging its advanced formal verification expertise for automotive and other high-integrity...
25 February, 2019
Article: HES-DVM Offers Enhanced Automation in FPGA Prototyping
Aldec’s HES-DVM 2018.2 automated and scalable hybrid verification environment for SoC and ASIC design offers enhanced automation in prototyping mode, plus faster HDL compilation....
22 February, 2019
Article: DVCon USA 2019 Preview: OneSpin
OneSpin will formally unveil its formal RISC-V Integrity Verification Solution for development and assessment of the open-source IP at DVCon next week....
22 February, 2019
Article: Using AI Data For Security
Pushing data processing to the edge has opened up new security risks, and lots of new opportunities....
21 February, 2019
Article: Partitioning Drives Architectural Considerations
Experts at the Table, part 2: Biggest tradeoffs in partitioning....
20 February, 2019
Article: Clock Domain Crossings In the FPGA World
Learn about clock domain crossing issues and overcoming them in FPGA designs....
06 February, 2019
Article: EDA Grabs Bigger Slice Of Chip Market
Manufacturing, packaging and development tools always have earned a fixed percentage of IC revenue, but that could change....
05 February, 2019
Article: Connectivity Checking Is A Perfect Fit For Formal Verification
Formal apps can target specific verification problems at a full-chip level, even on very large designs....
04 February, 2019
Article: Pushing AI Into The Mainstream
Why data scrubbing and social issues could limit the speed of adoption and the usefulness of this technology....
31 January, 2019