Article: Clock Domain Crossings In the FPGA World - FirstEDA
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Article: Clock Domain Crossings In the FPGA World

January 30th, 2019 – By: Aldec

 

 

Learn about clock domain crossing issues and overcoming them in FPGA designs.

 

Clock domain crossing (CDC) issues cause significant amount of failures in ASIC and FPGA devices. As FPGA complexity and performance grows, the influence of CDC issues on design functionality grows even more. This paper outlines CDC issues and their solutions for FPGA designs. Various design techniques are presented together with real-life examples for Xilinx and Intel FPGA devices. More importantly, this paper summarizes the most important CDC guidelines for highly-reliable FPGA designs.