Insight: Exploring An Open Source Risc-V Core - FirstEDA
22957
portfolio_page-template-default,single,single-portfolio_page,postid-22957,ajax_fade,page_not_loaded,,qode-child-theme-ver-1.0.0,qode-theme-ver-14.5,qode-theme-bridge,wpb-js-composer js-comp-ver-5.7,vc_responsive

Insight: Exploring An Open Source Risc-V Core

By Hendrik Eeckhaut

 

This weekend I read that Western Digital published the (System)Verilog sources of their Open Source Risc-V core on GitHub. Of course I wanted to try how easy it was to import this project in Sigasi Studio and test how well Sigasi Studio handles this code base.

 

I started by cloning the project….