Article: HES-DVM Offers Enhanced Automation in FPGA Prototyping

By Susan Nordyk


Aldec’s HES-DVM 2018.2 automated and scalable hybrid verification environment for SoC and ASIC design offers enhanced automation in prototyping mode, plus faster HDL compilation. This latest release provides design partitioning and partition interconnection tools designed to meet the growing need for prototyping FPGAs used as a pre-silicon SoC verification vehicle to ensure ultimate speed or as a hardware-software co-verification platform.


With the use of virtual partitions, HES-DVM can be used to design new prototyping boards to establish the most efficient board architecture for the project or with third-party and in-house developed FPGA boards. Release 2018-2 also boosts productivity with the addition of two automation enhancements.