Blog: Aldec Blog Post – Problems Accessing Registers? – See how UVM RAL can help.
Sunil Sahoo, Corporate Applications Engineer for Aldec, discusses the problems facing accessing registers, and how UVM RAL can help....
09 August, 2019
Archive
Article: Are Digital Twins Something For EDA To Pursue?
Part one: Defining the digital twins concept; the trouble with models; the issue with the ecosystem. ...
07 August, 2019
Article: A Holistic View Of RISC-V Verification
Successful projects entail more than core compliance to the ISA. ...
07 August, 2019
Article: AI/ML’s Role in ADAS
AI and machine learning advancements are evolving along with ADAS development. ...
06 August, 2019
Podcast: Swimming in the SoC
In this week’s episode of Fish Fry, we are swimming in SoCs! Rob van Blommestein (OneSpin) discusses the choppy waters of IC verification. Randy Fish...
31 July, 2019
Article: Hybrid Emulation Takes Centre Stage
Complex chips require a multitude of verification platforms working in sync, and that’s where the challenges begin. ...
25 July, 2019
Article: Hardware-Software Co-Design Reappears
There may be a second chance for co-design, but the same barriers also may get in the way. ...
25 July, 2019
Article: Partitioning Drives Architectural Considerations
Experts at the Table, part 3: Systems of subsystems; heterogeneous systems; re-partitioning. ...
19 July, 2019
Article: Breaking Down The Debug Process
Experts at the Table: Debug is not a monolithic task, and each stage in the processes needs a different focus. ...
17 July, 2019
Sigasi Studio v4.5 Preview
Sigasi Studio 4.5 Preview. Most important changes since the 4.4 release: Report error when a package has multiple package bodies, Better hover for procedures and...
15 July, 2019