Article: A Holistic View Of RISC-V Verification - FirstEDA
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Article: A Holistic View Of RISC-V Verification

August 7th, 2019 – By: Tom Anderson

 

Successful projects entail more than core compliance to the ISA.

 

Last month, we discussed the growth of the RISC-V open processor ecosystem, the two main organisations driving it, and the role that OneSpin plays. In addition, we have become very active in the RISC-V community and have more than a dozen technical articles published, conference talks presented, and upcoming talks accepted. We tend to focus on the challenges of verifying RISC-V IP cores and system-on-chip (SoC) designs containing these cores. Since I have been on the front line speaking at many of these conferences, I’d like to share my perspective on how the industry’s view of RISC-V verification is growing and evolving.

 

In the beginning, the whole idea of verification was focused on demonstrating compliance to the RISC-V Instruction Set Architecture (ISA) documents. The ISA is at the heart of the definition for any type of processor design. It defines the instructions, registers, flags, and the other elements that determine the capability of the design. There’s a lot of talk about compliance test suites to check that a RISC-V core matches the ISA. Such test suites are familiar to users of many types of design standards. They are sometimes provided by organisations supporting the standard as an aid to implementation and interoperability. There is clear value in multiple development teams verifying their designs with the same third-party compliance suite.