News Archive

Article: The Impact Of Moore’s Law Ending

Industry News, News Archive, Supplier News

PR: OneSpin Puts Verification on the Move with New PortableCoverage Solution

Industry News, Supplier News

Aldec News

PR: Aldec’s “Hardware and Software Co-verification in Hybrid Simulation and Emulation Environment with QEMU” DVCon Europe tutorial to demonstrate how engineers can obtain a holistic view over their SoC design

News Archive, Supplier News

PR: Hardware Safety Metrics for ISO 26262 Compliance

Industry News, Supplier News

Aldec News

Article: Visible Benefits

Featured News, Industry News, News Archive, Supplier News

Article: Domain Crossing Nightmares

Industry News, News Archive, Supplier News

Aldec News

WP: Clock Domain Crossings in the FPGA World

Featured News, Supplier News

FirstEDA Blog

Blog: FirstEDA Verification Series – Code Coverage

Blog

Article: Emulation in FPGA

Featured News, Industry News, Supplier News

Live Webinar: Boost VHDL Development Time with Background Design Rule Checking

Events, Featured News

Article: Which Verification Engine?

Featured News, Industry News, Supplier News

Article: Code Coverage within the HDL Editor – now that’s a nice feature

Featured News, Industry News, Supplier News

FirstEDA Blog

Blog: My “Advanced VHDL Testbenches & Verification” training experience

Blog, Featured News

Aldec News

PR: Aldec to Present Software Driven Test of FPGA Prototype

Featured News, Industry News, Supplier News

PR: Formal Verification Leader OneSpin Solutions Unveils its Comprehensive Safety Critical Solution for Automotive, Other Mission-Critical

Featured News, Industry News, Supplier News

Article: Jim Hogan rates all the EDA vendors on Safety Critical IC design

Featured News, Industry News

Article: Jim Hogan on using Formal along with random fault verification

Featured News, Industry News

Article: CEO Interview – Stanley Hyduke, founder and CEO of Aldec

Featured News, Industry News, Supplier News

Article: Jim Hogan on ISO 26262 certification and systematic verification

Featured News, Industry News

Article: Jim Hogan on how Safety Critical Verification is Next Big Thing

Featured News, Industry News

OSVVM: Making VHDL transaction-based testbenches simple, readable and powerful

Featured News, Industry News, Supplier News

Article: Why Auto Designs Take so Long

Featured News, Industry News, Supplier News

Job opening: Sales Engineer (HES)

Featured News, Industry News, Jobs

Aldec News

PR: Aldec Sets a New Paradigm with a Single Platform for DRC and CDC

Featured News, Industry News, Supplier News

Job opening: Business Development FRANCE

Featured News, Industry News, Jobs

Article: Sigasi – Cleaner VHDL and SystemVerilog

Featured News, Industry News, Supplier News

OSVVM: ASIC-level VHDL verification, simple enough for FPGAs

Featured News, Industry News, Supplier News

Aldec News

PR: Aldec Delivers DO-254 Compliant Environment with the Latest Release of Spec-TRACER

Featured News, Industry News, Supplier News

Advanced Verification training with OSVVM architect Jim Lewis

Featured News, Industry News

Video: Functional Safety and Formal Verification, with Dave Kelf of OneSpin Solutions

Featured News, Supplier News

Aldec News

PR: Aldec to Highlight ASIC Pre-Silicon Verification Spectrum

Featured News, Industry News, Supplier News

FirstEDA Blog

Blog: Design Rule Checking comes of age

Blog, Featured News