Code Coverage: An Introduction
As an important step in a metric driven verification process, code coverage provides a structural level check on the effectiveness of your tests. By collecting simulation data on the execution of each line of VHDL or Verilog, it can quickly highlight areas of your code that are not exercised.
By analysing the source code during simulation, detailed coverage data can be logged and then reported in a meaningful manner. Where coverage ‘holes’ exist, it normally indicates incomplete tests or unused code. As all untested code could contain bugs, they should be investigated.
Reflecting the underlying structure of HDLs, there are a number of code coverage classes that are of interest: statement, branch, condition & expression, toggle, path & FSM. Access to these is tool dependent – our Aldec simulators (Active-HDL & Riviera-PRO) provide full support!
Statement and branch are the most basic and I will be covering these in more detail in subsequent articles.
The reality is that 100% code coverage for any given design may be impractical due to hard constraints. Accordingly, the results can still be used as a ‘verification advisor’, guiding a design review to determine:
Ultimately, it’s for the design engineer, in conjunction with the verification engineer (if the roles are separated), to determine the sign-off criteria.
A simplified flow appears below (fig.1).
Fig1. Coverage analysis block diagram
As you can imagine, certain HDL constructs such as ‘if’ or ‘case’ embedded in statements or branches have a major bearing on the coverage results if they are not executed exhaustively. The same applies for condition and toggle coverage, where all subexpression combinations in complex branches needs to be exercised.
This is illustrated in the table below (fig.2), a representative breakdown for a first run.
Fig2. Example Summary of possible Initial Coverage Type results not reaching 100%
That’s the overview complete. In the next article I will be digging into statement coverage in more detail.
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