FPGA Design & Verification

/FPGA


We promote, support and can provide training for a number of highly efficient and cost-effective solutions for FPGA design and verification. These solutions provide excellent views over and into your designs and automate essential tasks.

FPGAs have come an incredibly long way since their introduction in the mid-1980s. While low gate-count devices are still used extensively at one end of the spectrum we now have broad availability of multi-million gate FPGAs with embedded processor cores. Accordingly, the automation of design and verification tasks is essential if projects are to be completed on time and, importantly, with confidence.

Aldec Active-HDL
FPGA Design & Simulation / FPGA / FV

Active-HDL is a Windows-based, integrated design creation and simulation solution for engineers working on projects ranging from simple PLD ‘glue logic’ all the way up to several-million-gate system-on-chip FPGAs.

Aldec ALINT-PRO
Advanced Design Rule Checking / FPGA / FV / SAFETY / ASIC

ALINT-PRO is a design rule checking (DRC) tool. It uses rule files (‘policies’) to check that a design’s RTL adheres to a defined RTL coding style. It decreases development time dramatically by identifying design issues early in the development schedule.

Aldec Riviera-PRO
Advanced Verification Platform / FPGA / FV / ASIC

Riviera-PRO addresses the verification requirements of engineers targeting large gate-count FPGAs, ASICs and System-on-Chip devices. It gives engineers the ultimate testbench in terms of productivity, reusability and automation; all by combining a high-performance simulation engine with advanced debugging capabilities (at different levels of abstraction).

Aldec ALINT-PRO-CDC
Advanced Design Rule Checking / FPGA / FV / SAFETY / ASIC

ALINT-PRO-CDC is a design verification solution focused on asynchronous clock domain crossing analysis and used to manage metastability in designs with multiple clock domains.

Aldec RTAX/RTSX
Prototyping Microsemi Rad Tolerant Devices / FPGA / PROTO

Aldec and Microsemi have joined forces to offer an innovative, reprogrammable prototyping solution for Microsemi RTAX-S/SL, RTAX-DSP and RTSX-SU space-fight system designs. Unlike the traditional One Time Programmable (OTP) anti-fuse space-qualified FPGAs, the Aldec prototype adaptor uses flash-based, Microsemi ProASIC 3E FPGA technology for design prototype re-programmability.

Sigasi Visual HDL
VHDL code editing, browsing & checking / FPGA / SAFETY / ASIC

Sigasi Visual HDL is an intelligent hardware design tool that features advanced programming assistance for engineers using HDLs for FPGA and ASIC design. This tool is valuable to anyone doing HDL design, and specifically engineering teams who create microchips for strictly regulated and safety critical environments.