The tool verifies the optimised design ‘as is’ without gate-level simulation, design modifications or design restrictions (such as disabling synthesis optimisations); and it verifies the whole-chip flat netlists, thus enabling the most aggressive optimisations and the creation of highly competitive designs.
360 EC-FPGA leverages OneSpin’s established formal technology with sequential FPGA verification capabilities.
It is an automatic, synthesis-tool-independent solution that verifies functional equivalence between the register transfer level (RTL) code and the post-synthesis netlist, as well as between the post-synthesis and post-place-and-route netlists. It eliminates the need for ‘side files’ generated by synthesis tools and extensive scripting.