Functional Equivalence Checking / FPGA / FV / SAFETY

360 EC-FPGA ensures systemic errors are not introduced in the RTL implementation process of programmable devices.

The tool verifies the optimised design ‘as is’ without gate-level simulation, design modifications or design restrictions (such as disabling synthesis optimisations); and it verifies the whole-chip flat netlists, thus enabling the most aggressive optimisations and the creation of highly competitive designs.


360 EC-FPGA leverages OneSpin’s established formal technology with sequential FPGA verification capabilities.


It is an automatic, synthesis-tool-independent solution that verifies functional equivalence between the register transfer level (RTL) code and the post-synthesis netlist, as well as between the post-synthesis and post-place-and-route netlists. It eliminates the need for ‘side files’ generated by synthesis tools and extensive scripting.


360 EC-FPGA solution is a formal equivalence checker that supports the sequential optimisations typical of FPGA implementation flows. This provides reduced risk for the project without compromising the QoR of the implemented design.

  • Works with major FPGA synthesis tools, including the Xilinx Vivado Design Suite and ISE, Synopsys Synplify, Altera Quartus II and Microsemi Libero SoC design tools
  • Supports all major FPGA device families from Xilinx, Microsemi and Altera, including (but not limited to):
    • Xilinx: Spartan-II, Spartan-IIE, Spartan-3, Spartan-XL, Spartan-6, Spartan-7, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5, Virtex-6, Virtex-7
    • Microsemi: Fusion, ProASIC3, ProASIC3E, ProASIC3L, IGLOO, IGLOOE, IglooPlus, Axcelerator, 54sx, 54sxa, ex, 3200dx, 40mx, 42mx, SmartFusion, SmartFusion2, IGLOO2
    • Altera : Cyclone, Cyclone II, Cyclone III, Hardcopy II, Stratix, Stratix GX, Stratix II, Stratix II GX, Stratix III, Stratix IV
  • Supports all sequential optimisations in FPGA synthesis, including constant registers, register duplication and merging, renaming of flip-flop instances, FSM optimisations, local retiming and pipelining
  • Supports device specific optimisations including DSPs, SRLs, distributed RAM, and block RAM
  • Verifies single FPGA, flat netlists and imposes no restrictions on netlist size
  • Supports RTL/gate and gate/gate equivalence checking
  • Supported design languages: Verilog, SystemVerilog, VHDL, EDIF and mixed languages
  • Supported computer platforms: Linux, Windows
At FirstEDA we have been working with European leading system companies that target programmable devices. We see the introduction of EC for FPGA to be an important addition for the validation of safety critical applications using programmable devices. As well as providing an exhaustive check, EC will identify errors quickly with the minimum of debug.