Blog: What goes around comes around

Many years ago, or so it seems, I designed and implemented my first programmable logic design. Not a multi-million gate equivalent FPGA, just a humble PAL (Programmable Array Logic). The simple 22v10 had twelve input pins, plus ten pins that could be user-programmed as either input or output, connected to a 132*44 programmable AND-array, with an Fmax of 250 MHZ. In the days of 7400 and 4000 discreet logic IC’s, this was a powerful tool in the engineer’s toolbox. If my memory serves me correctly, it was an interface chip to a VMEbus which used the PLD.

Today’s designs are much more challenging and the devices we use are considerably larger; take the Xilinx Zynq UltraScale+ devices for example, with up to 1,143K system logic cells and 668 IO pins. These are totally different beasts! Luckily they are supplied with multiple IP blocks which we can use to help rapidly develop our FPGA systems. Such devices are the pinnacle of what is available today and as these devices have evolved, so have design techniques, or have they?

My first PLD design utilised an early Hardware Description Language (HDL) called PALASM, and these days you probably use either VHDL or SystemVerilog HDL, but this was not always the case. The early FPGA development tools used schematic capture, until the design sizes became too unwieldy for this technique and we moved to HDLs plus synthesis. I have recently become aware of a new device however, the ForgeFPGA by Dialogue Semiconductor (A Renesas Company), which has a “Macro-cell Mode” design tool that uses a schematic-capture-based development flow. As they say in the UK, “what goes around comes around”.

As things evolve with design, so they need to with verification. In fact, verification has probably changed even more, as engineering teams try to find ways of making this phase of the development process more productive. It is widely accepted that verification can take 75% of your project timescale, so any improvements here can pay dividends. These days we see many different approaches to verification of designs. Using functional coverage with constrained random stimulus for example, as seen in UVM for SystemVerilog, OSVVM for VHDL, or Cocotb, which uses Python as opposed to an HDL. It is crucial to understand these different techniques, so that you are in the best position to apply the correct methodology to your current design verification project to get the best results.

Aldec has always been at the forefront of technological advances in design and verification for programmable logic designs, and shares this knowledge with us via its excellent webinar program. As we approach Christmas and the end of yet another year, why not update your knowledge by catching up on recent Aldec webinars, such as:

• UVM for FPGAs – A four-part series covering:
  • Get, Set, Go – Be Productive with UVM
  • Solving FPGA Verification Challenges with UVM
  • Verifying Zynq MPSoC Designs? Learn how UVM Register Access Layer (RAL) can help
  • IEEE 1800.2 UVM Updates
• Cocotb – The COroutine based COsimulation TestBench environment
  • Constraint Random Verification with Python and Cocotb
• OSVVM – The Open Source VHDL Verification Methodology
  • Creating an AXI4 Lite, Transaction Based VHDL Testbench with OSVVM
  • OSVVM: The New Stuff

So that’s it from me for 2021. I look forward to talking to you in 2022. Merry Christmas and Happy New Year!!