360 DV-Inspect


360 DV-INSPECT increases the productivity of existing design and verification flows by adding push-button formal analysis; which can start as soon as the design under test (DUT) has been compiled, and independently of testbenches. In this way, critical bugs can be found much earlier than with a purely simulation-based flow.

In addition, users can prove the absence of potential problems, such as synthesis-simulation mismatches, thus avoiding surprises later on in the design flow. While compiling the DUT, 360 DV-Inspect automatically synthesises assertions for numerous potential problems, such as violations of synthesis pragmas, write-write races, array index violations and resolution for X-values.


360 DV-Inspect provides static analysis to detect functional errors, typically employed as a “hand-off” requirement in the RTL development process.

  • Integrates easily into an existing design flow
  • VHDL, Verilog and SystemVerilog supported
  • Assertion synthesis is leveraged to generate comprehensive structural test sets and coverage analysis, further improving quality
  • A debug tool with simulation trace generator makes understanding issues easy
  • Share computationally heavy tasks over a network
  • Advanced debugging
  • Assertion synthesis for RTL clean-up
  • Assertion synthesis for code coverage
With push-button formal analysis, 360 DV-Inspect either finds a simulation trace from reset showing a violation of the assertion or it proves that the assertion cannot be violated. This is a major advantage in comparison to typical static linting tools – as they can only report potential problems rather than ensure that there is no real problem.
360 DV-Inspect is used by a number of FirstEDA’s customers, designing ASICs and safety critical applications using programmable devices.