Article: Chip Security Needs A New Language
SystemVerilog assertions can nicely capture many hardware requirements. However, more is needed for security verification. ...
27 August, 2019
Archive
Article: Synthesizing Hardware From Software
Can a software engineer create hardware? It may be possible but not in the way that existing high-level synthesis tools do it. ...
22 August, 2019
White Paper: Assuring the Integrity of RISC-V Cores and SOCs
This paper presents the OneSpin RISC-V Integrity Verification Solution and discussed how its components verify all four aspects of design integrity at both the processor...
22 August, 2019
Article: What Is A Custom Processor?
The definition has changed, and so has the impact on the design process. ...
22 August, 2019
Article: Debug Tools Are Improving
Experts at the Table: How is machine learning going to impact debug, and what other improvements are on tap with debug? ...
12 August, 2019
Article: Are Digital Twins Something For EDA To Pursue?
Part one: Defining the digital twins concept; the trouble with models; the issue with the ecosystem. ...
07 August, 2019
Article: A Holistic View Of RISC-V Verification
Successful projects entail more than core compliance to the ISA. ...
07 August, 2019
Article: AI/ML’s Role in ADAS
AI and machine learning advancements are evolving along with ADAS development. ...
06 August, 2019
Podcast: Swimming in the SoC
In this week’s episode of Fish Fry, we are swimming in SoCs! Rob van Blommestein (OneSpin) discusses the choppy waters of IC verification. Randy Fish...
31 July, 2019
Article: Hybrid Emulation Takes Centre Stage
Complex chips require a multitude of verification platforms working in sync, and that’s where the challenges begin. ...
25 July, 2019