FirstEDA Blog – Automated Code Coverage with VUnit and Riviera-PRO
OSVVM, not so much an application but a library and a methodology that our customers have been using to boost their design verification to the...
22 June, 2026
Archive
FirstEDA Blog – Building a Certification Ready Verification Flow for Safety-Critical FPGA Development
OSVVM, not so much an application but a library and a methodology that our customers have been using to boost their design verification to the...
21 May, 2026
FirstEDA Blog – Why VHDL Still Dominates FPGA Design in Europe; And Why Aligning Verification Makes Sense
OSVVM, not so much an application but a library and a methodology that our customers have been using to boost their design verification to the...
30 March, 2026
FirstEDA Blog – Unlocking the Power of Open-Source Verification Frameworks for ASIC, FPGA, and SoC Designs
OSVVM, not so much an application but a library and a methodology that our customers have been using to boost their design verification to the...
03 December, 2025
FirstEDA Blog – Optimising FPGA Development: From Design to Verification
OSVVM, not so much an application but a library and a methodology that our customers have been using to boost their design verification to the...
02 April, 2025
FirstEDA Blog – Riviera-PRO in the Dock
OSVVM, not so much an application but a library and a methodology that our customers have been using to boost their design verification to the...
13 December, 2023
Blog: Assertions in Aldec Riviera-PRO
Blog: Riviera-PRO as a Register Generator Tool ...
19 December, 2022
FirstEDA Blog – Raising the Bar on FPGA Verification
OSVVM, not so much an application but a library and a methodology that our customers have been using to boost their design verification to the...
03 March, 2022
Agnisys – Winding up an eventful year
Agnisys CEO Anupam Bakshi reflects on 2021...
04 January, 2022
Blog: Riviera-PRO as a Register Generator Tool
Blog: Riviera-PRO as a Register Generator Tool ...
13 December, 2021