FirstEDA Blog – Building a Certification Ready Verification Flow for Safety-Critical FPGA Development

Safety‑critical FPGA development is ultimately about trust. Not just trust in the design itself, but trust in the process that produced it. Whether working under DO‑254, ISO 26262, IEC 61508 or similar standards, engineering teams must demonstrate that their FPGA designs are structurally sound, functionally correct, and verified with objective, auditable evidence. Over the years, we’ve seen many teams struggle to balance these demands with the practical realities of development: limited time, limited resources, and the desire to avoid overly complex methodologies.

At FirstEDA, we support organisations across Northern Europe, working with engineering teams in aerospace, defence, automotive and industrial markets. Despite the diversity of applications, these teams consistently face the same challenge: they need a verification flow that is rigorous enough for certification, yet efficient and maintainable enough for real‑world engineering. The combination of Sigasi Visual HDL, Aldec ALINT‑PRO, OSVVM, and Riviera‑PRO has proven to be one of the most effective ways to achieve that balance. Each tool plays a distinct role, but together they create a cohesive, certification‑ready verification ecosystem.

Starting with Quality: Sigasi Visual HDL

High‑quality verification begins with high‑quality RTL, and this is where Sigasi Visual HDL makes a profound difference. Instead of treating HDL as plain text, Sigasi brings modern IDE capabilities to VHDL and SystemVerilog development. Engineers benefit from real‑time error detection, intelligent code analysis, and instant navigation across large codebases. The result is cleaner, more maintainable RTL written from the outset, with far fewer issues slipping through to later stages.

For safety‑critical teams, this matters enormously. Code readability improves design reviews. Automatic documentation generation supports traceability. Visualisation of hierarchy and state machines helps engineers and auditors alike understand the design intent. By the time the RTL reaches static analysis, it is already in a far better state; reducing rework and accelerating the entire verification process.

Establishing Structural Integrity: ALINT‑PRO

Once the RTL is written, ALINT‑PRO becomes the first automated verification checkpoint. Static analysis is essential in safety‑critical development because it catches structural issues that simulation may never reveal. ALINT‑PRO applies rule sets tailored for standards such as DO‑254 and ISO 26262, helping engineers demonstrate adherence  to safe coding practices and deterministic behaviour.

Clock‑domain and reset‑domain crossing analysis, FSM checks, latch detection, and reset‑initialisation verification all contribute to a clear picture of the design’s structural health. Importantly, ALINT‑PRO produces detailed, exportable reports that slot neatly into certification evidence packages. By resolving structural issues early, teams avoid costly late‑stage debugging and give simulation a more solid starting point .

Modern VHDL Verification Without the Overhead: OSVVM

With the RTL structurally validated, attention shifts to functional verification. Many safety‑critical teams prefer to stay within VHDL for clarity, determinism, and ease of review. OSVVM (Open Source VHDL Verification Methodology) enables them to do exactly that while still benefiting from modern verification capabilities.

OSVVM provides constrained‑random stimulus generation, functional coverage modelling, scoreboards, self‑checking testbenches, and transaction‑level modelling; all within a pure VHDL environment. This avoids the complexity of SystemVerilog/UVM while still enabling scalable, maintainable verification architectures. For certification, this simplicity is a major advantage: fewer languages, fewer tools, and fewer moving parts to justify.

Verification Closure with Confidence: Riviera‑PRO

Riviera‑PRO is the engine that drives the dynamic verification process. It executes OSVVM testbenches, captures coverage metrics, and provides the advanced debugging capabilities needed to reach verification closure. Engineers can explore waveforms, analyse transactions, inspect assertions, and run regressions with confidence that the results are both accurate and auditable.

Coverage (both code and functional) is central to certification. Riviera‑PRO integrates seamlessly with OSVVM’s coverage models and provides detailed reports that demonstrate verification completeness. Combined with regression management and automation features, it ensures that every requirement is exercised, every coverage point is closed, and every result is documented.

A Cohesive, Certification‑Ready Flow

What makes this toolchain so effective is the way each component feeds naturally into the next. Sigasi Visual HDL ensures that the RTL is clean, readable and well‑structured from the moment it is written. ALINT‑PRO validates that structure against safety‑critical standards, catching issues that simulation cannot. OSVVM provides a modern, VHDL‑native methodology for building robust testbenches. Riviera‑PRO executes those testbenches, collects coverage, and produces the evidence required for verification closure.

The result is a flow that is both technically rigorous and practically achievable. It produces evidence that can be traced from requirements to verification results. It reduces rework by catching issues early. It avoids unnecessary complexity while still delivering advanced verification capabilities. And most importantly, it produces the artefacts that certification bodies expect to see.

Supporting Safety‑Critical Teams Across Northern Europe

FirstEDA are the Northern European distributor for both Aldec and Sigasi. We are also the trusted partner of SynthWorks, a training company led by the OSVVM co-founder and principal architect, Jim Lewis. As such, FirstEDA is uniquely positioned to help teams adopt and refine this verification flow. We provide not only the tools, but also the expertise to integrate them effectively into existing processes. Whether you are starting a new safety‑critical project or strengthening an established workflow, this combination of Sigasi Visual HDL, ALINT‑PRO, OSVVM and Riviera‑PRO offers a powerful, efficient and certification‑ready foundation.

If you’d like to explore how this flow could support your next project, we’d be delighted to discuss your requirements.