Tom Anderson, OneSpin Solutions Applying formal verification to thoroughly verify a RISC-V processor design. Not so long ago, many semiconductor and system suppliers developed their own processors,...
Mark Christiaens, Head of Engineering Sigasi...
The consumer revolution over the past few decades has funnelled a growth of SoC chips primarily in the area of consumer electronics....
Michelle Mata is an Applications Engineer at Aldec focusing on Hardware Emulation Solutions. She received her B.S. in Computer Engineering from the University of Nevada,...
We are pleased to announce that Aldec's flagship RTL simulator Riviera-PRO now supports SweRV! The makefile that includes Riviera-PRO has now been merged into the...
Together with EASA, Airbus, Thales and other leading avionics regulatory experts and system suppliers, Aldec will be presenting at the Certification Together International Conference (CTIC)...
Aldec and Codasip at Embedded World: Showcasing an Integrated UVM Simulation Environment for Verifying Custom Instructions with RISC-V Cores....
Getting a unified look at what formal, simulation, and acceleration/emulation contribute to verification....
Using an embedded prototyping board to reduce system bring-up time and simplify customisation efforts....
Open-source growth predictions are impressive, but the verification process can be harder than with commercial ISAs....