Release: Aldec and Codasip at Embedded World: Showcasing an Integrated UVM Simulation Environment for Verifying Custom Instructions with RISC-V Cores - FirstEDA
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Release: Aldec and Codasip at Embedded World: Showcasing an Integrated UVM Simulation Environment for Verifying Custom Instructions with RISC-V Cores

19 February 2020

Nuremberg, Germany – Aldec, a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, is exhibiting at Embedded World in Nuremberg, Germany on February 25-27, 2020. Aldec and Codasip will be showcasing an integrated UVM simulation environment for verifying custom instructions with RISC-V cores.

By integrating Aldec’s Riviera-PRO with Codasip’s Studio, verification of custom instructions at the RTL implementation level becomes an incredibly powerful platform for RISC-V processor deployment…