Blog: Jim Lewis – OSVVM, The #1 VHDL Verification Library
Open Source VHDL Verification Methodology (OSVVM) has been named the number #1 VHDL Verification Library by The 2018 Wilson Research Group Study....
03 July, 2019
Archive
Blog: Sigasi – Hardware Design Made Easier, More Efficient And More Fun
Sigasi Studio is a HDL code checker, editor and browser. This blog shows some of the key features of Sigasi Studio and how they can...
03 July, 2019
Blog: Design Rule Checking – How Early is Early?
Our application specialist outlines the importance of early design analysis in his methodology to reduce uncertainty during the debugging phase of verification....
18 June, 2019
Blog: Aldec Blog Post – 35-years-old, and still on point
Aldec's Hardware General Manager, Zibi Zalewski, talks about his trip to this year's Design Automation Conference held in Las Vegas, June 3-5....
18 June, 2019
Blog: Time flies when you’re having fun
Read Adam Wilson’s blog which gives an insight into his latest trips to FPGA-forum in Trondheim, and La Palma for Sigasi's annual company meeting....
08 May, 2019
Blog: Aldec Blog Post – No Risk No Fun.
Janusz Kitel, DO-254 Programme Manager, reflects on attending a recent Aerospace show and it's apparent lack of emphasis on safety....
14 March, 2019
Blog: Earning my stripes at my first industry conference
Last month I took the opportunity to embark on my first international business trip. For someone like me, who for various reasons has not travelled...
06 November, 2018
Blog: FirstEDA Verification Series – Code Coverage
As an important step in a metric driven verification process, code coverage provides a structural level check on the effectiveness of your tests. By collecting...
01 December, 2017
Blog: My “Advanced VHDL Testbenches & Verification” training experience
[vc_row css_animation="" row_type="row" use_row_as_full_screen_section="no" type="full_width" angled_section="no" text_align="left" background_image_as_pattern="without_pattern"][vc_column width="1/6"][vc_single_image image="22548" qode_css_animation=""][vc_column_text]Kevin Nugent FirstEDA[/vc_column_text][/vc_column][vc_column width="5/6"][vc_column_text]With all the hype surrounding competing verification methodologies, it's time for a cool...
14 October, 2017
Blog: Design Rule Checking comes of age
As with so many EDA products that are now in mainstream use in FPGA design & verification, their early roots were in the ASIC flow....
10 October, 2016