Blog: Aldec Blog Post – Do I really need a commercial simulator?
Sunil Sahoo discusses the benefits of having a commercial simulator, as opposed to using vendor-provided 'free' simulation tools....
11 October, 2019
Archive
Release: Aldec’s Focus for Arm TechCon is on Deep Neural Network and Machine Learning Application Development
Aldec will be exhibiting at Arm TechCon (October 8-10, San Jose, California, USA) and demonstrating solutions that stand to aid greatly in the development of...
03 October, 2019
Article: Assessing The Safety Of Automotive Chips
ASICs, FPGAs and SoCs are at risk for errors during operation. FMEDA is crucial for the analysis of default risk. Is automation possible? ...
30 September, 2019
Article: Automated connectivity checking with formal verification
Given a sufficiently robust set of properties to describe intended behaviour, formal tools can not only find all bugs but also prove that there are...
26 September, 2019
Article: High-Level Design And High-Level Verification
Expectations for C++/SystemC designs must be set properly. ...
26 September, 2019
Article: The Growing Impact Of Portable Stimulus
Experts at the Table: How the Portable Test and Stimulus Standard has affected the industry and who are the early adopters? ...
26 September, 2019
Release: Aldec cuts ASIC design prototype bring-up time with HES-DVM’s automatic partitioning tool and faster HDL-to-FPGA compilation times
The 2019.09 release of HES-DVM provides fast compilation and FPGA partitioning automation, aiding greatly in design setup for physical prototyping on multi-FPGA boards from Aldec...
24 September, 2019
Sigasi Studio v4.5 Released
Sigasi Studio 4.5 release, where Sigasi Studio’s editor became a lot faster, as in up to 3 times faster. We also added HTML documentation, and...
20 September, 2019
Article: FPGA Design Tradeoffs Getting Tougher
As chips grow in size, optimizing performance and power requires a bunch of new options and methodology changes. ...
16 September, 2019
Blog: Aldec Blog Post – HW/SW Co-Simulation for SoC FPGA designs
Aldec’s Co-Simulation Solution using QEMU and Riviera-PRO...
10 September, 2019