Functional Verification

/FV


Due to the complexity of today’s designs, effective verification is an essential requirement in ensuring rapid detection and rectification of issues early in the design cycle. Whatever techniques you use to functionally verify your latest design, be it HDL simulation or formal methods, we have the tools and methodologies that you require to succeed.

As designs have grown larger the requirement for efficient and effective functional verification has also swelled, with the needs to verify multiple IP blocks and processor blocks adding to the complexity of verification.

Aldec Active-HDL
FPGA Design & Simulation / FPGA / FV

Active-HDL is a Windows-based, integrated design creation and simulation solution for engineers working on projects ranging from simple PLD ‘glue logic’ all the way up to several-million-gate system-on-chip FPGAs.

Aldec ALINT-PRO
Advanced Design Rule Checking / FPGA / FV / SAFETY / ASIC

ALINT-PRO is a design rule checking (DRC) tool. It uses rule files (‘policies’) to check that a design’s RTL adheres to a defined RTL coding style. It decreases development time dramatically by identifying design issues early in the development schedule.

Aldec Riviera-PRO
Advanced Verification Platform / FPGA / FV / ASIC

Riviera-PRO addresses the verification requirements of engineers targeting large gate-count FPGAs, ASICs and System-on-Chip devices. It gives engineers the ultimate testbench in terms of productivity, reusability and automation; all by combining a high-performance simulation engine with advanced debugging capabilities (at different levels of abstraction).

Aldec ALINT-PRO-CDC
Advanced Design Rule Checking / FPGA / FV / SAFETY / ASIC

ALINT-PRO-CDC is a design verification solution focused on asynchronous clock domain crossing analysis and used to manage metastability in designs with multiple clock domains.