Riviera-PRO is a high performance, high capacity, multi-language simulator that provides a unified debug environment for VHDL, Verilog, SystemVerilog, SystemC and PSL. The core simulation engine includes advanced simulation optimisation for both VHDL & Verilog simulation.
As well as supporting traditional HDL verification techniques, Riviera-PRO provides advanced analysis and debug capabilities for UVM and TLM verification methodologies.
Riviera-PRO provides project and workspace capability as well as script-based operation for compilation and simulation.
High Performance Simulation
Industry’s Best ROI