Blog: Aldec Blog Post – Unit Linting: An easy way to prevent code review issues
Sunil Sahoo discusses the benefits of doing code reviews from the beginning by using Unit Linting....
11 October, 2019
Archive
Blog: Aldec Blog Post – Do I really need a commercial simulator?
Sunil Sahoo discusses the benefits of having a commercial simulator, as opposed to using vendor-provided 'free' simulation tools....
11 October, 2019
Blog: Aldec Blog Post – HW/SW Co-Simulation for SoC FPGA designs
Aldec’s Co-Simulation Solution using QEMU and Riviera-PRO...
10 September, 2019
Blog: Aldec Blog Post – Problems Accessing Registers? – See how UVM RAL can help.
Sunil Sahoo, Corporate Applications Engineer for Aldec, discusses the problems facing accessing registers, and how UVM RAL can help....
09 August, 2019
Blog: Jim Lewis – OSVVM, The #1 VHDL Verification Library
Open Source VHDL Verification Methodology (OSVVM) has been named the number #1 VHDL Verification Library by The 2018 Wilson Research Group Study....
03 July, 2019
Blog: Design Rule Checking – How Early is Early?
Our application specialist outlines the importance of early design analysis in his methodology to reduce uncertainty during the debugging phase of verification....
18 June, 2019
Blog: Aldec Blog Post – No Risk No Fun.
Janusz Kitel, DO-254 Programme Manager, reflects on attending a recent Aerospace show and it's apparent lack of emphasis on safety....
14 March, 2019
Blog: FirstEDA Verification Series – Code Coverage
As an important step in a metric driven verification process, code coverage provides a structural level check on the effectiveness of your tests. By collecting...
01 December, 2017