Blog: VHDL Training with a difference
Adam Wilson discusses VHDL training, and how FirstEDA are different from the rest....
15 November, 2019
Archive
Blog: Agnisys Blog Post – Creating Test Sequences for RISC-V Cores and SoCs
Louie De Luna discusses creating test sequences for RISC-V cores and SoCs...
11 November, 2019
Blog: Aldec Blog Post – HW/SW Co-Verification Environment for Hybrid Systems Using QEMU
Aldec's Senior Hardware Systems Designer Wojtek Lewandowski discusses HW/SW Co-Verification Environment for Hybrid Systems Using QEMU...
01 November, 2019
Blog: Jim Lewis Blog – OSVVM at #DVConEurope
Transaction-Based Testing with OSVVM and the OSVVM Model Library at #DVConEurope...
30 October, 2019
Blog: Aldec Blog Post – Unit Linting: An easy way to prevent code review issues
Sunil Sahoo discusses the benefits of doing code reviews from the beginning by using Unit Linting....
11 October, 2019
Blog: Aldec Blog Post – Trace Your Assertions
Katarzyna Hrynkiewicz discusses assertions and their importance in EDA, and how at Aldec they have something which helps overcome any reservations towards assertions....
11 October, 2019
Blog: Aldec Blog Post – Do I really need a commercial simulator?
Sunil Sahoo discusses the benefits of having a commercial simulator, as opposed to using vendor-provided 'free' simulation tools....
11 October, 2019
Blog: Aldec Blog Post – HW/SW Co-Simulation for SoC FPGA designs
Aldec’s Co-Simulation Solution using QEMU and Riviera-PRO...
10 September, 2019
Blog: Aldec Blog Post – FPGA vs GPU for Machine Learning Applications: Which one is better?
Aldec's Applications Engineer, Farhad Fallahlalehzari, discusses whether FPGAs beat GPUs? And which is better for Machine Learning Applications....
12 August, 2019
Blog: Aldec Blog Post – Problems Accessing Registers? – See how UVM RAL can help.
Sunil Sahoo, Corporate Applications Engineer for Aldec, discusses the problems facing accessing registers, and how UVM RAL can help....
09 August, 2019