Blog: The summer is coming
Read Adam Wilson’s blog which talks about spending time to review and improve on your FPGA design and verification tool flow and methodology....
29 June, 2020
Archive
Blog: What is still missing in your FPGA design verification methodology?
In this blog, Nomita introduces the consideration of introducing formal methods and assertion-based verification into your FPGA verification methodology....
22 June, 2020
Blog: Windows ate my Signal Browser
This blog explains solving a problem for an Active-HDL customer....
15 June, 2020
Blog: Making Giant Leaps
An analogy as to why you need a methodology in a complex FPGA design to catch issues early in the design flow to avoid long...
08 June, 2020
Blog: Active-HDL Hints & Tips
This blog explains solving a problem for an Active-HDL customer....
02 June, 2020
Blog: Code Coverage and Functional Coverage – What’s the Difference?
This blog explores differences between Code Coverage and Functional Coverage with particular focus using Aldec’s Riviera-PRO with SystemVerilog constructs...
14 May, 2020
Blog: Methodology: A must for complex FPGA design
This blog looks into how to achieve better coverage using VHDL and the features of OSVVM....
01 May, 2020
Blog: Achieving Better Coverage with VHDL – Part 1
This blog looks into how to achieve better coverage using VHDL and the features of OSVVM....
17 April, 2020
Blog: Jim Lewis Blog – OSVVM gone Apache … on the path to IEEE Open Source
In the latest release of Open Source VHDL Verification Methodology (OSVVM), all licenses for the entire OSVVM library (utility and model libraries) were updated to...
21 January, 2020
Blog: An Introduction to Assertion-Based Verification – Part 2
In part 2 we will develop the use of implication in assertions and its importance in assertions, as well as use in simulation....
20 January, 2020